1. Field of the Invention
The present invention generally relates to integrated circuit devices, and more particularly, the present invention relates to the input/output (I/O) interface of an integrated circuit device.
2. Description of the Related Art
It is generally desirable to increase the data transfer bandwidth at the input/output (I/O) interface of integrated circuit (IC) devices. Unfortunately, however, any increase in transfer bandwidth is accompanied by an increase in the number of data pins of the IC device. A large number of data pins disadvantageously occupy a large device area, and also increase power consumption and power related noise.
FIG. 1 is a block diagram of a conventional memory circuit. Address signals ADDR1–ADDRi are temporarily stored by an address buffer 10, and a clock signal CLK and external command signals /CS, /RAS, /CAS and /WE are applied to a command decoder 20. At a timing of the clock signal CLK, the command decoder decodes the external command signals into internal command signals PR, PC, PREAD, and PWRITE. In response to the internal command PR, the row decoder 30 selects one or more rows of a memory cell array 50 according to an address stored in the address buffer 10. Likewise, in response to the internal command PC, the column decoder 40 selects one or more columns of the memory cell array 50 according to the address stored in the address buffer 10. Whether data is written into or read from the memory cell array 50 is controlled by the internal commands PWRITE and PREAD, respectively. Data read from the memory cell array is passed through an I/O interface circuit 55 and applied to data pins DQ1 through DQn, and data written into the memory cell array 50 is received from the data pins DQ1 through DQn via the I/O interface circuit 55.
FIG. 2 is a detailed block diagram of the interface circuit 55 shown in FIG. 1. In the case of a read operation, a first bit DATA1 of the n-bit parallel output data is temporarily stored in an output buffer 55-1 and then applied to the data pin DQ1. Similarly, second and third bits DATA2 and DATA 3 of the n-bit parallel output data are temporarily stored in output buffers 55-3 and 55-5, and then applied to the data pins DQ2 and DQ3, respectively. The remaining bits of the parallel output data are likewise temporarily stored in respective n−3 buffers (not shown) and then applied to data pins DQ4 through DQn of FIG. 1.
In the case of a write operation, a first bit of the n-bit parallel input data at data pin DQ1 is temporarily stored in an input buffer 55-2 and then applied as DATA1 to the memory cell array. Likewise, second and third bits of the n-bit parallel input data at the data pins DQ2 and DQ3 are temporarily stored in input buffers 55-4 and 55-6 and then applied as DATA2 and DATA 3 to the memory cell array. The remaining bits of the parallel input data at data pins DQ4 through DQn of FIG. 1 are also temporarily stored in respective n−3 input buffers (not shown) and then applied to the memory cell array.
The data DATA1, DATA2, etc. are deemed to be logically high (H) or low (L) depending on the voltage level thereof. FIG. 3 is a diagram for explaining the two-level signaling scheme of the conventional I/O interface circuit. If the voltage level of the input data is greater than a reference voltage REF, then the input data is deemed to be logically high (VIH), and if the voltage level of the output data is greater than the reference voltage REF, then the output data is also deemed to be logically high (VOH). On the other hand, if the voltage level of the input data is less than the reference voltage REF, then the input data is deemed to be logically low (VIL), and if the voltage level of the output data is less than the reference voltage REF, then the output data is also deemed to be logically low (VOL).
In the conventional device described above, the number of data pins DQ1 through DQn is equal to the number of bits of the parallel input/output data read from and written into the memory cell array. Thus, any increase in the number of bits of the data transfer rate of the I/O interface will result the need to additionally equip the device with an equal number of data pins. As suggested previously, any addition in the number of data pins disadvantageously occupies more device area, and also increases power consumption and power-related noise.